Software developer with vast experience in the development of C++ based large scale software tools in the domain of VLSI-EDA. Experienced in both digital tools such as timing/power analysis and circuit optimization as well as analog tools and in the application of mathematical optimization techniques including linear and convex optimization.
I am interested in application of optimization (linear, convex, and discrete) and regression methods to all classes of engineering problem including machine learning applications.
Software Architect at Cadence Design Systems
I am part of the Tempus team that develops a static timing analysis tool to verify the performance of microprocessor designs with hundreds of millions of timing elements. I am responsible for developing and implementing features to perform hierarchical timing analysis on large designs and involves creating timing models of blocks that are as small as possible while retaining the timing information that can be used to verify the timing of other blocks in the design hierarchy accurately.