Masters in Electrical Engineering with a major in IC Design and Verification and minor in Signal Integrity from Portland State University.
In-depth knowledge and experience in: Design Verification using UVM(Functional Verification, Constraint random Verification), SystemVerilog Assertions, Computer Architecture, VLSI design, Physical Design (RTL to GDSII), ASIC/FPGA development flow, DFT, SOC, Logic design, Synthesis, Validation, Scripting, Low Area, Low Power, Place and Route (P&R) and Static Timing Analysis (STA)
– Proficient in concepts of ISI, crosstalk, jitter, eye diagrams, and how to alleviate them on a platform.
– Experience with Design of Experiment using JMP tool
– Hands on experience in using lab equipment such as VNA, Spectrum Analyzer, Infrared Scanner, Power meter, and Signal Generator, Oscilloscopes
– Extremely adept and comfortable working with groups to ensure project success.
– Very result oriented working philosophy with great attention to details.
– Excellent technical documenting abilities to help define, finalize, and record process flow and details.
- Basic Python
- Verilog/System Verilog
September 2015 May 2017
Masters in Electrical and Computer Engineering at Portland State University
October 2017 June 2018
Hardware Engineer at eSwara LLC